Data Addressing Modes of 8086

     1. Immediate Addressing Mode

In this mode, 8 or 16 bit data(operand) can be specified as part of the instruction.

____________________________________

|      OP Code        |      Immediate Operand   |

|______________|_____________________|

Example: MOV CL, 03H

              = Moves the 8 bit data  03H into CL

                MOV DX, 0525H

              = Moves the 16 bit data 0525H into DX

A constant value such as "VALUE" can be defined by the assembler EQUATE directive such as

  

              VALUE EQU 35H

Example: MOV BH, VALUE

             = Used to load 35H into BH

     2. Register Addressing Mode

The operand to be accessed is specified as residing in an internal register of 8086.

Example: MOV DX, CX

             = Move 16 bit content of CX into DX

                MOV CL, DL

             = moves 8 bit content of DL into CL

     3. Direct Addressing Mode

The instruction Opcode is followed by an Effective Address(EA), this effective address is directly used as the 16 bit offset of the storage location of the operand from the location specified by the current value in the selected segment register.

The default segment is always DS.

PA= DS:EA

Segment override prefix (SOP)

PA =  _    _

          | CS | 

          | DS |      :         [ Direct Address ]

          |  SS |

          |  ES |

          --    -- 

     4. Register Indirect Addressing Mode

The EA is specified in either pointer(BX) register or an index (SI or DI) register. The 20 bit physical address is computed using DS and EA.

Example: MOV [DI], BX

             If [DS] = 5004, [DI]=0020, [BX]=2456, PA=[50060]

             The content of BX is moved to memory locations 50060H and 50061H.

               MOV AL, [START+BX]

              The 8 bit content of this memory location is moved to AL.

               The kind of addressing used in this particular example is known as Based Addressing Mode,                since BX pointer is used. 

               

               Indexed Addressing Mode: MOV BH, START [SI]

                                                         Here Physical Address(PA) will be [START]+[SI]+[DS]

               Based Indexed Addressing Mode: MOV ALPHA[SI][BX], CL

                                                         Here PA will be ALPHA+[SI]+[BX]+[DS]

     5. Input-Output Mode (Direct):

Here port number is an 8-bit immediate operand.

Example: OUT 05H, AL

                Outputs [AL] to 8-bit port 05H.

          Input-Output (Indirect):

The port number is taken from DX.

Example: IN AL, DX

              If [DX] = 5040,

              8 bit content by port 5040 is moved to AL.

     6. Relative Addressing Mode

Example: JNC START

             If CY=0, then PC is loaded with current PC contents plus 8 bt signed value of START,                        otherwise the next instruction is executed.

     7. Implied Addressing Mode

Instruction using this operating mode have no operands.

Example: CLC which clears the carry flag.

Importance Of Segmentation

-The segment:offset scheme requires only a 16bit number to represent the base address for a segment and only 16bit offset to access any location in a segment.

- This means that the 8086 has to manipulate and store only 16 bit quantities instead of 20bit quantities.
This makes for an easier interface with 8 and 16bit wide memory boards and with the 16 bit registers in the 8086.

- Each time the CPU switches from one user's program to the next, it must access a new section of data. Segmentation makes this switching quite easy.

The Execution Unit

8086 Internal Architecture

Control Circuitry, Instruction Decoder And ALU

- The Execution Unit (EU) contains circuitry which directs internal operations.

- A decoder in the EU translates instructions fetched from memory into a series of actions which the EU carries out.

- The EU has AND, OR, XOR, increment, decrement, complement or shift binary numbers.

Flag Register

- A flag is a flip-flop which indicates some condition produced by the EU of an instruction or controls certain operations of the EU.

- A 16-bit flag register in the EU contains 9 active flags.

- 6 of 9 flags are used to indicate some condition produced by an instruction.

- The six additional flags in this group are:-
  + Carry Flag (CF)
  + Parity Flag (PF)
  + Auxiliary Carry Flag (AF)
  + Zero Flag (ZF)
  + Sign Flag (SF)
  + Overflow flag (OF)

- The 3 other flags in the flag register are used to control certain operations of the processor.
These flags are different from six conditional flags described above in the way they are set or reset.

- The six conditional flags are set or reset by the EU on the basis of the results of some arithmetic or logic operation.

- The control flag is deliberately set or reset with specific instructions you put in your program.

- The 3 control flags are:-
   + Trap Flag (TF): which is used for single stepping through a program.
   + Intrupt Flag (IF): which is used to allow or prohibit the intruption of a program; and
   + Direction Flag (DF): which is used with string instructions.

General Purpose Registers

- EU has 8 general purpose registers, labelled AH, AL, BH, BL, CH, CL, DH and DL.

- These registers can be used individually for storage of 8-bit data.

- AL register is also called ACCUMULATOR.

- Certain pairs of general purpose registers can be used together to store 16-bit data words. Eg: AH & AL, BH & BL, CH & CL, DH & DL.

- AH & AL pair is reffered as AX register. Similarly, BH & BL pair is reffered as BX; CH & CL pair is reffered as CX; DH & DL is reffered as DX register.

- The 8086 general purpose register set was designed this way so that many programs written for 8080 and 8085 microprocessor could easily be translated to run on the 8086.

- The advantage of using internal registers for the temporary storage of data is that, since data is already in EU, it can be accessed much more quickly than it could be accessed from external memory.

8086 Flag Register Format

- Carry Flag- Set(1) by carry out of Most Significant Bit.

- Parity flag- Parity is a term used to indicate whether a binary word has an even number of 1(s) or an odd number of 1(s). A binary number with an even number of 1(s) is said to have even parity.

- Auxiliary Flag- It has significance in BCD addition or BCD addition or BCD subtraction. If a carry is produced when the least significant nibbles of 2 bytes are added, the flag will be Set. If subtraction of least significant nibbles requires a borrow then the auxiliary carry/borrow flag will be set.

- Zero Flag- It is set to 1 if the result of an arithmetic/logic operation is zero.

- Sign Flag- The sign flag is a copy of MSB of the destination byte or the destination word. Here, 0 is for positive and 1 is for negative. This flag can be used to determine whether an operand has been decremented beyond zero.

- Trap Flag- single step trap flag.

- Interrupt Enable Flag- Enabled/Disabled based on the Intrupt acceptation state.

- Direction Flag- Used for Strings

- Overflow Flag- This flag will be set if the result of a signed operation is too large to fit in the number of bits available to represent it.

The Bus Interface Unit

8086 Internal Architecture

The Queue

- While the EU is decoding an instruction or executing an instruction which does not require use of the buses, the BIU fetches upto 6 instruction byte for the following instructions.

- The BIU stores these pre-fetched bytes in a first in first out register set called Queue.

- When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction from the queue in the BIU.

- This is much faster than sending out an address to the system memory and waiting for memory to send back the next instruction byte or bytes.

- Fetching the next instruction while the current instruction executes is called Pipelining.

Segment Registers

- The 8086 BIU sends out 20 bit addresses, so it can address any of 2^20 bytes in memory.

- However, at any given time the 8086 works with only 4 segments within this 1 Mb range.

- Four segment registers in the BIU are used to hold the upper 16 bits of the starting address of four memory segments that the 8086 is working with at a particular time.

- The four segment registers are:-
   + Code Segment (CS) register:
                                                    The register contains the initial address of the code segment. The address plus the offset value contained in the Instruction Pointer(IP) indicates the address of an instruction to be fetched for execution.

   + Stack Segment (SS) register:
                                                    The initial address of the stack segment plus value in the Stack Pointer(SP) is used for stack operations.

   + Extra Segment (ES) register:
                                                    ES is used by some string operations. Contains initial address of the extra segment. String instructions always use ES and Destination Index(DI) registers to calculate the physical address for the destination.

   + Data Segment (DS) register:
                                                  The initial address of the current data segment address plus offset value in instruction causes a reference to a specific location in the data segment.

- The BIU always inserts zeros for the lowest 4 bits (nibble) of the 20bit starting address for segment.
For example: if the Code Segment register contains 348AH, then the code segment will start at 348A0H.

- This constraint was put on the location of Segment so that it is only necessary to store and manipulate 16 bit numbers when working with the starting address of a segment.

- The part of a segment starting address stored in a segment register is often called the Segment Base.

- A stack is a section of memory set aside to store address and data while a subprogram executes.

- The extra Segment register and the data Segment register are used to hold the upper 16 bits of the starting address of 2 memory segments that are used for data.

One way four 64Kb segments might be positioned within the 1 Mb address space of an 8086.

Instruction Pointer

- The instruction pointer register holds the 16-bit address, or offset of the next code byte within this code segment.
- The value contained in the IP is reffered to as an offset because this value must be offset from(added to) the segment base address in CS to produce the required 20bit physical address sent out by the BIU.

Addition of IP to CS to produce the physical address of the code byte

- An alternative way of representing a 20bit physical address is the segment base:offset form. For the address of a code byte, the format for this alternative form will be CS:IP. Eg: 348A:4214

Stack Segment Register and Stack Pointer Register

- The 8086 allows you to set aside an entire 64Kb segment as stack. The upper 16 bits of the starting address for this segment are kept in the stack segment register.

- The Stack Pointer(SP) register in the execution unit holds the 16bit offset from the start of the segment to the memory location where a word was most recently stored on the stack.

- The memory location where a word was most recently stored is called the top of the stack.

Addition of SS and SP to produce the physical address of the top of the stack

- The physical address can also be represented as SS:SP i.e. 5000:FFE0H.

Execution Unit

Pointer and Index Registers in The Execution Unit

- In addition to the stack pointer register(SP), the EU contains a 16 bit base pointer(BP) register.

- It also contains 16bit source index(SI) register and a 16 bit destination index (DI) register.

- Those 3 register can be used for temporary storage of data just as the general purpose registers.

- However, their main purpose(use) is to hold the 16bit offset of a data word in one of the segments.

- The physical address of the data in memory is given by adding SI to DS.

8086 Internal Architecture

- The 8086 CPU is divided into two independent functional parts, the Bus Interface Unit or BIU and the Execution Unit or EU.

- Dividing the work between these two units speeds up processing.

- The BIU has the following functionalities;
   + It sends out addresses
   + It fetches instructions from memory
   + It reads data from parts and memory; and
   + It writes data to ports and memory.

- In other words, the BIU handles all transfers of data and addresses on the buses for the execution unit.

- The execution unit of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions and executes instructions.

8086 Internal Architecture